`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/09/04 11:41:22
// Design Name: 
// Module Name: station
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module station(
    input clk,
    input rst,
    input valid_s,
    input [3:0] data_s,
    input ready_d,
    output reg valid_d,
    output reg [3:0] data_d,
    output ready_s
    );
    
    wire handshake;
    
    assign handshake = ready_s && valid_s;
    assign ready_s = ready_d || ~valid_d;
    
    always @(posedge clk)
    begin
        if (rst) 
        begin
            valid_d <= 0;
        end
        else
        begin
            valid_d <= ready_s ? valid_s : valid_d;
        end
    end
    
    always @(posedge clk)
    begin
        if (rst) 
        begin
            data_d <= 0;
        end
        else
        begin
            data_d <= handshake ? data_s : data_d;
        end
    end                

endmodule

